Overview As part of the Infinity Fabric Architecture and RTL team, you will define microarchitecture and implement synthesizable RTL for on chip interconnect that links CPUs, GPUs and accelerators. You will work across Austin and global sites to deliver high quality hardware in a fast, collaborative environment. The role emphasizes scalable NoC/fabric components, performance tuning and cross team coordination. You will also leverage modern tools, including AI-assisted approaches, to boost design quality and productivity.
Responsibilities- Define microarchitecture for interconnect (fabric / network-on-chip) components
- Develop and implement synthesizable RTL using Verilog/SystemVerilog
- Optimize designs to meet power, performance, area, and timing goals
- Contribute to scalable, coherent interconnect solutions across multiple product lines
- Collaborate with architecture, verification, and cross-functional engineering teams
- Support unit-level validation and deliver high-quality RTL to verification teams
- Develop assertions and contribute to coverage strategies
- Debug design issues during pre-silicon and post-silicon phases
- Create clear and maintainable design documentation
Key requirements- Experience with RTL design using Verilog or SystemVerilog
- Background in interconnect, network-on-chip (NoC), or cache/memory subsystem design
- Understanding of processor architecture, including coherency and memory systems
- Knowledge of digital design fundamentals and high-speed hardware systems
- Experience debugging RTL or hardware systems
- Familiarity with power, performance, and area tradeoffs
- Exposure to scripting or programming languages such as Python, C, or C++
- Awareness of design-for-test (DFT) concepts
- Familiarity with x86 or ARM architectures is helpful
- Interest in using AI-assisted tools to improve design and debugging workflows
- Collaborative mindset
- Clear communication across cross-functional teams
- Ownership and accountability
- Verilog
- SystemVerilog
- NoC/interconnect design
