Overview As a SoC Analog & Mixed-Signal Design Engineer, you design and optimize analog and mixed-signal circuits for advanced CMOS processes, contributing across the design lifecycle to deliver robust IP that meets power, performance, area, timing, and yield targets. You collaborate with architecture, layout, and engineering teams to address circuit challenges and enable high-quality silicon solutions. The role centers on solving complex analog/mixed-signal problems and driving efficient, reliable designs for next-generation Intel products. This is a hands-on, cross-functional role with a strong impact on product performance.
Compensation / Benefits- competitive compensation with stock bonuses
- health and retirement benefits
- vacation and work-life balance
Responsibilities- Design, develop, and build analog circuits in advanced CMOS process nodes
- Create floorplans, perform circuit design, extract chip parameters, and simulate analog behavior models
- Develop and execute test plans to verify designs against specifications
- Evaluate test results, optimize circuits for power, performance, area, timing, and yield
- Collaborate cross-functionally to report progress and address issues
- Minimize leakage and enhance area efficiency of analog/mixed-signal blocks
- Work with architecture and layout teams to ensure robust functionality and electrical capabilities
Key requirements- Bachelor in Electrical Engineering, Electronics, or related field with 4+ years of analog circuit design experience OR Master with 2+ years OR PhD with 1+ related experience
- Experience with analog simulation tools and methodologies
- Experience with circuit optimization techniques focused on power, area, timing, and yield
- Experience with advanced process nodes in analog design
- Technical Problem-Solving
- Design Ownership
- Collaboration
- Analog/mixed-signal IC or SoC design in advanced CMOS process technologies
- Circuit design and optimization across operating conditions and corners
- Low-power circuit design, leakage reduction, and power optimization
