Overview In this role you will join a global design/verification team to advance CAD flows for CMOS IC layout and design. You'll evaluate and enhance in-house and commercial EDA tools, and drive productivity across design, layout, and verification teams. You will conduct R&D on next-generation CAD software and implement flows that improve efficiency and cost. This position offers cross-functional collaboration and opportunities to shape tooling that supports memory design at scale.
Compensation / Benefits- medical, dental and vision plans
- paid time-off
- paid holidays
- income protection during illness/injury
- paid family leave
- Benefits Guide available on
Responsibilities- Develop tools, flows, and methodologies to boost productivity and reliability of memory designs
- Integrate commercial EDA tools into design flows
- Provide training, documentation, and end-user support on new tools and methods
- Collaborate with design, layout, verification and process teams
- Undertake R&D of next-generation CAD software to meet product development needs
- Identify deficiencies in current tools and flows and propose improvements
- Understand EDA offerings and trends to seize performance and efficiency opportunities
- Evaluate tools with internal customers and define improved flows for efficiency and cost
- Develop, maintain and support engineering infrastructure
Key requirements- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science with 5+ years of industry experience
- Strong programming fundamentals with Unix and shell scripting
- Good knowledge of CMOS circuits, deep-submicron physical design, CMOS manufacturing, and layout design rules
- collaboration with cross-functional teams
- training and knowledge sharing
- strong communication and documentation
- Calibre DRC/LVS, floorplanning, automated P&R, SPF extraction
- Verilog, Verilog-A, ncverilog, VCS, Spice/FastSpice, FineSim/PrimeSim, HSPICE
- RTL-to-GDS flows
