Overview In this role you will drive FPGA/ASIC verification for Packet-Optical Platform solutions at Ciena. You will establish verification methodology and infrastructure, work with design teams to set priorities, and execute comprehensive test plans and regression. You'll contribute to both chip- and block-level verification, ensuring product quality at scale. This opportunity lets you shape verification strategy in a collaborative, innovation-driven environment.
Compensation / Benefits- medical, dental, and vision plans
- 401(K) with company matching (USA) and DCPP (Canada)
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- paid holidays, sick leave, and vacation
- paid Family Leave and other leaves of absence
Responsibilities- Establish verification methodology, architecture, and infrastructure (models, generators, monitors, scoreboards)
- Collaborate with design team to define test priorities and coverage targets
- Create verification plans
- Create and execute test cases
- Create and maintain regression suites and provide verification reports
- Participate in chip-level verification activities for FPGA designs
- Participate in block-level verification activities for FPGA designs
Key requirements- Minimum 2+ years as FPGA/ASIC verification engineer
- Development of testbench environments using SystemVerilog and UVM
- Directed and constrained-random stimulus generation
- Strong problem solving and debugging skills
- Ability to prioritize work and meet FPGA design timelines
- Experience with PCIe, I2C, and SPI interfaces; Ethernet packet structures/interfaces (CAUI, XLAUI, XAUI, XFI)
- Experience with Mentor Graphics and/or Synopsys verification tools
- Excellent verbal and written communication skills
- Ability to work independently and in a team environment
- Excellent interpersonal and team skills
- SystemVerilog
- UVM
- Directed and constrained-random stimulus
