Overview As a Principal Physical Design Engineer, you will help shape Microsoft's next gen AI SOCs by delivering robust physical design flows and sign offs. You'll lead PnR, timing, and verification activities across blocks to subchips, while developing methodologies that boost efficiency and performance. You'll collaborate with cross functional teams to ensure on time, high quality silicon for cloud services, and mentor junior engineers to raise design quality. This role offers a strong impact on scalable, energy efficient hardware for Microsoft's AI and cloud platform.
Responsibilities- Lead PnR convergence recipe development for blocks/subsystems and subchips
- Develop methodologies to improve physical design efficiency and performance
- Sign off on blocks/subsystems/subchips in STA, PV, FEV, ECOs, low power verification
- Implement functional and timing ECOs with minimal PD impact
- Design and implement global clocking schemes at SOC/subchip levels
- Stay current with industry trends to improve PD processes
- Install and quality check internal/external IP collaterals for PD use
- Conduct PD reviews and guide junior engineers
Key requirements- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's in AND 6+ years OR Bachelor's in AND 8+ years OR equivalent experience
- Strong background in physical design and chip timing/verification
- Experience with PnR, STA, PV, FEV, ECOs, EM/IR drop
- Experience with global clocking, IP collaterals, and PD infrastructure
- Ability to lead projects and mentor teammates
- Security background checks and export control compliance
- Experience with PD EDA tools and scripting (TCL, Python)
- Foundry tech files and rule decks understanding
- Tapeouts of complex ASICs is a plus
- leadership
- mentoring
- collaboration
- PnR (Place and Route)
- Static Timing Analysis (STA)
- Physical Verification (PV)
