Overview In this role, you will lead verification for advanced memory interface products at Renesas, enabling reliable DDR6 and future generations for data center, AI, and cloud workloads. You will shape verification strategy, develop SystemVerilog/UVM environments, and drive coverage closure across complex designs. You will collaborate across engineering teams to ensure functional and performance goals are met, while mentoring others and delivering reusable verification solutions. This is a high-impact position at a global semiconductor leader with a strong focus on cutting-edge memory interfaces.
Compensation / Benefits- medical
- health savings account
- dental
- vision
- flexible spending accounts
- paid holidays
Responsibilities- Provide technical leadership for verification of complex semiconductor designs at block and system level
- Define and drive verification strategies, test plans, and coverage approaches
- Develop and optimize SystemVerilog/UVM verification environments and testbenches
- Drive verification execution, functional coverage, debugging, and closure of coverage goals
- Own significant verification efforts and make independent technical decisions on methods and priorities
- Collaborate with design engineers and stakeholders to validate functional and performance requirements
- Analyze verification and design issues, identify root causes, and drive solutions
- Develop reusable verification methodologies and best practices for broader use
- Participate in architecture, feasibility, design, and technical reviews
- Mentor and provide guidance to verification engineers across projects and levels
- Coordinate with cross-team stakeholders to meet milestones and objectives
- Communicate verification status, risks, and recommendations to leadership and stakeholders
Key requirements- 10+ years of experience in semiconductor design verification
- Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM
- Experience defining verification strategies and developing verification plans from specifications
- Strong experience developing, optimizing, and debugging UVM-based environments and testbenches
- Strong experience with functional verification, coverage, checkers, test development, debugging, and coverage closure
- Ability to independently resolve complex technical problems and guide verification methodologies
- Proven track record of providing technical guidance and mentorship to engineers
- technical leadership
- mentorship
- strong communication
- SystemVerilog
- UVM (Universal Verification Methodology)
- verification strategy development
