Overview In this role you will shape advanced high-bandwidth memory interfaces, leading architecture and implementation from definition to silicon bring-up. You will work across cross-functional teams (package, interposer, SI/PI, thermal) to optimize HBM-based subsystems for AI, ML, and HPC workloads. You'll drive performance, reliability, and manufacturability while mentoring engineers and steering multi-team programs. This is a hands-on, impact-focused position at a world-leader shaping memory technology.
Compensation / Benefits- medical, dental and vision plans
- paid time-off
- paid holidays
- paid family leave
- benefits guide available on
Responsibilities- Own and deliver critical HBM IO blocks and subsystems from architectural definition through tape-out, bring-up, and post-silicon debug
- Define HBM PHY, controller-to-PHY, die-to-die interfaces, clocking, training, calibration, power-management, error handling, and test requirements
- Balance bandwidth, latency, power, area, reliability, yield, and manufacturability across high-performance memory subsystems
- Lead architecture and design of analog, mixed-signal, and digital interfaces for memory subsystems
- Collaborate with package, interposer, physical design, SI, PI, and thermal teams for 2.5D/3D optimization
- Lead root-cause analysis for pre- and post-silicon issues across domains
- Serve as technical project lead for advanced interface programs coordinating multiple teams
- Define and communicate technical priorities, specs, plans, risks, and schedules
- Work with internal teams, customers, IP providers, foundries, and ecosystem partners on high-speed memory solutions
- Research and influence next-gen HBM, CPO, chiplet, and heterogeneous architectures for AI/ML/HPC
- Apply deep knowledge of DRAM, HBM/DDR, JEDEC, mixed-signal, and high-speed interfaces to architect scalable solutions
- Mentor engineers through architecture and build reviews to improve methods, IP reuse, and execution
Key requirements- 18+ years of experience in HBM/DDR/LPDDR or advanced memory/high-speed PHY roles
- Proven experience delivering complex interface IP/subsystems from architecture to silicon bring-up and post-silicon debug
- Strong expertise in high-speed memory-interface architecture and HBM product families (preferred)
- Extensive analog and mixed-signal circuit design, digital microarchitecture, RTL design, clocking, training, calibration, power management, and error handling
- Experience with frontend implementation and verification: synthesis, static timing analysis, LEC, RTL debug
- Demonstrated technical project leadership across multidisciplinary teams
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field
- Strong communication skills to explain complex concepts to engineers, leaders, customers, and ecosystem partners
- Mentorship and team leadership
- Technical initiative and collaborative problem-solving
- HBM PHYs and DDR/LPDDR PHYs (direct experience preferred)
- CPO system architecture, optical-electrical interfaces, silicon-photonics integration, or high-speed SerDes
- UCIe or other die-to-die interfaces and chiplet architectures
