Overview In this role you will design and verify ASIC solutions for Cisco's CHG platforms, contributing to silicon architecture, RTL implementation, and post-silicon validation. You will collaborate across verification and physical design teams to meet timing, power, and performance goals, shaping next gen AI-era hardware. This position offers hands-on influence over critical silicon projects and opportunities to work on Silicon One and related platforms.
Compensation / Benefits- Medical, dental, and vision insurance
- 401(k) plan with Cisco matching
- Paid parental leave
- Paid time off (holidays, vacation, sick leave)
- Volunteer days
- Restricted stock units eligibility
Responsibilities- Author design specifications and participate in micro-architecture specification reviews
- Implement Verilog RTL to meet timing, performance, and power requirements
- Develop and analyze functional coverage
- Collaborate with the verification team to address design corner cases and close coverage
- Work closely with physical design to close timing and place-and-route issues
- Perform diagnostic and post-silicon validation tests in the lab
Key requirements- Bachelor's in Electrical or Computer Engineering with 7+ years of ASIC design experience, or Master's in Electrical or Computer Engineering with 4+ years, or PhD with 1 year of ASIC design experience
- Experience with Verilog/SystemVerilog
- At least one full ASIC tapeout (advanced nodes preferred)
- Strong RTL skills with timing closure, power, clock gating, and full ASIC design flow
- Solid debugging and scripting skills
- Good written and verbal communication skills
- Good written and verbal communication skills
- Collaboration with cross-functional teams
- Verilog/SystemVerilog
- Timing closure
- Power management and clock gating
- Full ASIC design flow
