Overview In this role you will lead architecture work for chip-to-chip NVLink interconnects, guiding requirements and collaboration across research, design, and software teams. You'll model, validate, and document NVLink interfaces and fabric performance, defining flows and configurations for scalable, secure communication. You'll drive implementation across design, verification, firmware, and software to deliver next-generation interconnect technology. This is a hands-on, cross-functional leadership role at the forefront of high-speed chip interconnects, with a strong impact on NVIDIA's modular ecosystem and performance leadership.
Compensation / Benefits- equity
- benefits
- salary transparency
Responsibilities- Research and craft architecture solutions for chip-to-chip communication, optimizing performance, area, power, security, and resiliency
- Define interfaces and data/control flows between NVLink blocks and the rest of the chip
- Architectural modeling, validation, documentation
- Drive implementation across design, verification, firmware and software teams
- Collaborate with switch teams to define NVLink fabric architecture
- Define network configuration and management flows
Key requirements- MS or PhD in Electrical Engineering, Computer Science or Computer Engineering (or equivalent experience)
- At least 8+ years of relevant experience in architecture, design, and verification
- Hands-on experience with innovative ASIC design processes
- Shipped multiple projects and strong in processor and I/O architecture
- Programming in C++, Verilog
- Self-starter able to work in a small dynamic team
- self-starter
- autonomous
- ability to work in a small dynamic team
- C++
- Verilog
- ASIC design processes
