Overview In this role you will verify complex digital designs, focusing on TPU architecture and its AI/ML integration. You will build and enhance constrained-random verification environments and work with design engineers to identify key scenarios. You'll develop and maintain coverage to reveal verification gaps and drive progress toward tape-out. You collaborate across teams to define verification plans, debug tests, and contribute to silicon bring-up for data-center accelerators. This is a hands-on, impact-driven role shaping Google's TPU technology and hyperscale AI infrastructure.
Compensation / Benefits- bonus target
- equity
- benefits
- career growth
- industry-leading projects
Responsibilities- Plan verification strategy for complex digital blocks and collaborate with design engineers to identify critical scenarios
- Create and refine constrained-random verification environments using SystemVerilog and UVM
- Develop all types of coverage measures for stimulus and corner cases
- Debug tests with design engineers to ensure functionally correct designs
- Close coverage gaps and track progress toward tape-out
- Verify RTL digital logic for ASICs using SystemVerilog/UVM
- Contribute to architecture, verification planning, and silicon bring-up of TPUs and data-center accelerators
Key requirements- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 8 years of experience with design verification
- Experience verifying digital logic at RTL using SystemVerilog/UVM for ASICs
- collaborative
- problem-solving
- strong communication
- SystemVerilog
- UVM
- constrained-random verification
