Overview In this role you will drive reliability design enablement for Intel's PDK/TFM ecosystem to optimize power, performance and area. You'll partner with PDK development, EDA vendors and internal teams to deliver robust design rules, QA, and benchmarking. You will shape industry-leading PDKs, design collateral, and IP ecosystems to support design on Intel technology. You'll work in a cross-functional, fast-moving environment to enable reliable, high-quality designs.
Compensation / Benefits- health, dental, and retirement benefits
- 14 paid holidays per calendar year
- three weeks of paid vacation
- four-week paid sabbatical every four years
- five bonuses per year dependent on performance
- employee stock purchase program
Responsibilities- Define and generate reliability-related PDK design rules and collateral, including QA and benchmarking
- Lead EDA tool/flow enablement in alignment with PDK development; collaborate with internal teams and vendors to deliver competitive TFM
- Plan and deliver industry-leading PDK, design rules, collateral, TFM, and IP ecosystem for internal/external design on Intel tech
- Support design reliability verification through rigorous analysis and continuous improvement
Key requirements- Bachelor in Electrical Engineering, Physics, or related field
- 6+ years of relevant experience or 4+ years with a master's or PhD with 2+ years of relevant experience
- 3+ years in PDK development, reliability tool/flow, design for reliability, or related validation
- Hands-on experience with PDK development and validation; knowledge of PDK fundamentals and reliability rules
- Ability to use programming or scripting to support design rule generation and QA
- excellent written and verbal communication
- detail-oriented with a quality-driven mindset
- ability to drive quality enhancements projects
- PDK development and validation
- reliability tool and flow
- design for reliability
