Overview In this role you contribute to Teradyne's next-generation large mixed-signal ASICs within the Silicon Technology Engineering group. You collaborate with chip architects and analog teams to shape RTL and micro-architecture across life-cycle phases, from spec to silicon bring-up. You'll work with a best-in-class digital team and leverage AI tools to boost productivity, while ensuring first-pass silicon success. This is an impact role focused on enabling advanced SOC and memory test instruments at scale.
Compensation / Benefits- comprehensive health benefits
- dental and vision coverage
- Flexible Spending Accounts
- retirement savings plans
- life and disability insurance
- paid vacation and holidays
Responsibilities- Develop specifications, micro-architecture, and RTL for mission-critical blocks in collaboration with the chip architect
- Integrate standard and Teradyne IPs
- Collaborate with verification to finalize test plans, debugging, and coverage for RTL and silicon success
- Provide timing constraints and STA support to the Physical Design team through timing closure
- Support post-silicon lab bring-up and debugging
Key requirements- Bachelor in Electrical Engineering or related field with 5+ years of experience
- Extensive RTL design experience in Verilog
- Experience designing state machines, FIFOs, high-speed data paths, and arbitration logic including DFT
- Experience with logic synthesis and timing constraints
- Experience with clock domain crossings (CDC) and static timing analysis (STA)
- Experience with high-speed memory and serial interfaces
- Automation through scripting (Python, Tcl, Make)
- Collaborative teamwork
- Customer-focused mindset
- Detail-oriented debugging and problem-solving
- Verilog RTL
- State machines and FIFOs
- High-speed data paths and arbitration logic
