Overview As a Principal ASIC Design Engineer at Micron, you own the digital block architecture and RTL implementation for high-speed interface tech, partnering with analog and layout teams to bring designs from architecture to silicon. You shape timing, CDC, and verification strategies on a lean, senior team focused on front-to-back tape-out. You will collaborate across RTL, verification, and physical implementation to ensure robust, scalable digital blocks for advanced memory/AI-enabled systems. This role offers hands-on ownership with immediate impact in a cutting-edge PHY program.
Compensation / Benefits- medical, dental, and vision plans
- paid time-off and paid holidays
- bonus and equity potential
- competitive base salary
- comprehensive benefits guide in careers page
- wellbeing and professional growth programs
Responsibilities- Own digital block architecture and RTL implementation for DSP-like blocks (CSR/register file, clocking logic, management interfaces, state machines)
- Define and document architecture specs and interface control documents; serve as reference for digital design
- Define CDC strategy and ensure closure with analysis tools
- Coordinate with analog/design teams for chip integration and partitioning
- Perform logic synthesis and optimization toward PPA targets
- Maintain block-level SDC constraints and perform timing analysis across corners/modes
- Act as digital interface to layout team with synthesized netlists, constraints, floorplanning input
- Review floorplan decisions, provide timing feedback, and assist RTL/constraints issue resolution
- Coordinate with verification team on scan/DFT and ATPG planning
- Self-verify RTL with block-level simulation and waveform debugging; write SVA for control sequences and protocol compliance
- Collaborate on verification plan, testbench coverage, and bug resolution
- Support GLS and timing via released netlists and parasitics; assist lab bring-up with waveforms
- Document block specs, SDC rationale, implementation guidance, and ECO history
Key requirements- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
- 7-12 years of ASIC design with at least one complete front-to-back tape-out
- Proficiency in synthesizable SystemVerilog RTL design with clean coding practices
- Hands-on logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)
- Proficiency in RTL simulation and debug (VCS or Xcelium; Verdi or DVE) for block-level self-verification
- Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)
- Ability to interface between digital design and custom/analog teams and translate design intent
- Strong written communication skills for specifications and documentation
- Proficiency with AI tools for design, debugging, and documentation workflows
- Strong written communication
- Cross-functional collaboration
- Hands-on problem solving
- SystemVerilog RTL design
- Synopsys Design Compiler or Cadence Genus
- PrimeTime or Tempus
