Overview As Senior Product Engineering Manager, you lead a cross-functional team to bring FPGA and SoC products to market, shaping next-gen devices and manufacturing plans. You will work within the FPGA Business Unit to drive qualification, yield improvements, and fast-rollout while collaborating with engineering, quality, marketing, and operations. This role offers high-impact work at scale in a multi-billion-dollar global organization that values growth, trust, and innovation. You'll own key milestones from development to production ramp and customer adoption.
Compensation / Benefits- health benefits from day one
- retirement savings plans
- restricted stock units (RSUs)
- quarterly bonus payments
- industry-leading ESPP with 2-year look-back
- competitive base pay
Responsibilities- Lead the Product Engineering team and drive growth through internal development and strategic hiring
- Define manufacturing plans for next-generation FPGA and SOC lines
- Plan and execute qualification activities for advanced FPGA and SoC products
- Supervise test limit validation, yield enhancement, and failure analysis for rapid rollout
- Champion offshore bring-up, address yield issues, and implement corrective actions to meet revenue goals
- Drive continuous innovation to improve yields, quality, and time to market
- Enable customer shipments and support requests to accelerate technology adoption and revenue ramp
Key requirements- 15+ years of experience in Electrical engineering
- At least 10 years in a leadership/managerial role
- Deep knowledge of solid-state physics, silicon reliability, and failure mechanisms
- 5+ years in SOC product qualifications (JEDEC)
- Hands-on with data management tools/languages like KLA and JMP
- Understanding of SoC and FPGA architectures and FPGA software design suites
- Excellent written and verbal communication; collaborative leadership style
- Data-driven, proactive, strategic thinker with strong problem-solving skills
- collaborative leadership
- strong communication
- problem-solving
- SoC and FPGA architectures
- JADEC qualification processes
- test yield optimization
