Overview As an ASIC Design Engineer on AWS' Cloud-Scale Machine Learning Acceleration team, you design and optimize RTL hardware for high-performance, power-efficient ML inference systems such as AWS Inferentia. You will balance features, speed, area, and power through microarchitectures and SystemVerilog RTL, collaborating with cross-functional teams to deliver robust, scalable silicon. This role offers the chance to shape next-generation accelerators in a fast-paced data-center environment and contribute to AWS' leadership in ML hardware. You'll work on impactful problems at scale, defining architecture trade-offs and driving design quality.
Compensation / Benefits- health insurance (medical, dental, vision)
- 401(k) matching
- paid time off
- parenteral leave
- RSUs
- flexible working arrangements
Responsibilities- Develop high-performance, area- and power-efficient RTL designs meeting project specs
- Analyze designs, microarchitectures, and architectures to optimize feature, power, performance, and area trade-offs
- Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with constraints
- Perform lint and clock domain crossing checks to ensure design integrity
- Collaborate with architects, designers, verification, pre- and post-silicon validation, and back-end teams
Key requirements- Bachelor's degree or equivalent
- 3+ years of non-internship design or architecture experience for new and existing systems
- Learn and Be Curious mindset
- ability to collaborate with cross-functional teams
- strong analytical and problem-solving skills
- SystemVerilog
- RTL design
- Synthesis and timing closure
