Overview In this role, you will partner with cross-functional teams to architect and verify advanced DFT solutions for high-performance CPU designs. You will pioneer custom DFT methods using standard EDA tools to speed test turnaround and coverage, and develop production test patterns for ATE flows. You will mentor peers and help align DFT work with Google's hardware and AI ambitions, delivering scalable silicon that powers consumer products. This is a hands-on, impact-focused role at the frontier of silicon bring-up and test engineering.
Compensation / Benefits- 15% bonus target
- equity
- benefits
Responsibilities- Architect, implement, and verify DFT solutions for advanced CPU designs
- Pioneer custom DFT methodologies using industry-standard EDA tools
- Develop, debug, and optimize production test patterns for ATE flows
- Mentor peers and foster cross-functional collaboration within DFT
Key requirements- Bachelor's degree in Electrical Engineering or related field; equivalent practical experience
- 8 years of experience in high-performance IP or SoC DFT activities and flows
- Experience developing, deploying, and supporting DFT flows (ATPG, Logic Vision, BIST, or JTAG)
- Cross-functional collaboration
- Mentoring and leadership
- Strong communication
- DFT flows (ATPG, Logic Vision, BIST, JTAG)
- Industry-standard EDA tools
- Automation scripting in Python, Tcl, or Perl
