Overview In this role you will architect DFT solutions for LEO chip SOCs and work across ASIC, RFIC, and test teams to meet fault coverage, timing, and power targets. You will contribute to AI-enabled DFT workflows and help translate ATE patterns into tester formats. You will collaborate with design and test engineers to bring up digital portions of the LEO chips. This position offers a chance to shape advanced wireless silicon for satellite gateways and contribute to high-impact, cross-site initiatives.
Compensation / Benefits- health insurance (medical, dental, vision)
- 401(k) matching
- paid time off
- parential leave
- RSUs
- sign-on payments
Responsibilities- Architect and define DFT solutions for various LEO chips
- Improve and customize IPs and DFT methodology with AI flow
- Collaborate with ASIC design teams to integrate DFT logic (MBIST, clock controls, JTAG)
- Coordinate with RFIC teams to maximize fault coverage on RF blocks
- Ensure blocks meet DFT, timing, and power targets with implementation teams
- Assist Test engineering to translate ATE patterns to tester formats
- Jointly bring up digital portions of LEO chips
Key requirements- Bachelor in Electrical/Communications Engineering or equivalent experience
- 5+ years in advanced DFT techniques for deep sub-micron nodes
- Experience implementing DFT methodology and developing automated scripts for insertion and validation
- DFT techniques for deep sub-micron nodes
- MBIST and JTAG integration
- Clock controls and DFT logic insertion
- AI/ML-based automation for DFT workflows
- Experience with RFIC collaboration on mixed-signal chips
- Automated scripting for DFT insertion/validation
