Overview In this role you will help advance Micron's memory technologies by developing physical verification tools, flows, and methodologies for next gen DRAM, HBM, and emerging memories. You will work closely with design, layout, verification, modeling, and process teams to implement robust verification strategies and ensure successful tape outs. You will build rule decks and guide design teams on DRC/DFM/LVS/PERC checks while evaluating EDA tools to improve quality, performance, and efficiency. This position combines hands on CAD development with cross functional collaboration to scale advanced memory designs.
Compensation / Benefits- medical, dental, and vision plans
- paid time off
- paid holidays
- paid family leave
Responsibilities- Develop Physical Verification tools, flows, and methodologies for next gen memory designs (DRAM, HBM, emerging memories)
- Collaborate with design, layout, verification, modeling, and process teams to implement product development and verification strategies
- Build verification rule decks and guide design teams on DRC/DFM/LVS/PERC methodologies and checks
- Evaluate EDA tool offerings to improve quality, performance, and efficiency in processes
Key requirements- 10+ years of CAD or Physical Verification rule deck (DRC/LVS) development experience
- Deep understanding of physical verification methodologies, flows, and quality metrics
- 5+ years of CMOS circuit design, layout, and verification experience
- 5+ years of layout automation in Virtuoso using SKILL or Python
- Bachelor or Master in Computer Science, Computer Engineering, Electrical Engineering, or Electronics Engineering or equivalent experience
- Outstanding communication
- Problem-solving skills
- Ambitious to continuously learn and self-improve
- Physical verification methodologies, flows, and quality metrics
- CMOS circuit design, layout, and verification
- Layout automation in Virtuoso using SKILL or Python
