Overview In this role you drive timing convergence for multi-million-gate designs on advanced nodes and partner with cross-functional teams through signoff and tapeout. You'll leverage STA expertise to tighten constraints, debug timing issues, and deliver successful tapeouts in a collaborative environment. You join a mission-driven team building a high-performance AI platform, where your work directly impacts performance, area efficiency, and project timelines. This opportunity combines hands-on timing work with automation and AI-enabled flow improvements to scale design delivery.
Compensation / Benefits- competitive compensation package
- hybrid work arrangement
- benefits
Responsibilities- Drive timing convergence across blocks, partitions, and top-level designs and publish timing models
- Analyze timing violations and implement fixes to maintain progress toward tapeout
- Develop and validate bottom-up constraints with Design and DFT teams for closure requirements
- Collaborate across distributed teams to update methodologies and drive signoff readiness
- Create automation and flow enhancements using Python, Perl, and Tcl; leverage SPICE, PNR, CTS, routing, and DFT concepts as applicable
Key requirements- 8+ years of experience in STA, timing closure, and advanced-node design implementation
- Experience with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff
- Proficient in writing and debugging SDC constraints, ECOs, and worst-case corner analysis
- Strong collaboration and communication skills across cross-functional teams
- collaboration
- communication
- results-driven
- STA and timing closure
- advanced-node design implementation
- constraints scripting (SDC)
