Overview In this role you will design and validate high-performance memories for Arm CPUs, GPUs and SoCs. You will collaborate with a cross-functional memory development team to explore multiple foundries and deep submicron technologies, shaping memory architectures and features. You will contribute across the memory development flow, from specification to QA, with a focus on performance, power and area targets. Leveraging AI-driven scripting, you will improve design efficiency and quality while delivering memory solutions for next gen devices. This is a rare chance to impact core technology across Arm's product family in a collaborative, innovation driven environment.
Compensation / Benefits- salary range disclosed
- accommodations during recruitment
- hybrid working model
- equal opportunity employer
- diverse and inclusive environment
Responsibilities- Study memory architectures and development flows
- Perform transistor-level full-custom design and coordinate with layout teams
- Develop new memory features and optimize designs for performance, power, and area on advanced nodes (3 nm+)
- Contribute to design specification, circuit design, margining, physical verification, memory characterization, FE verification, release, and QA for CPU/GPU/SoC memories
- Create and maintain AI-powered scripts to improve execution efficiency and quality
- Ensure high-quality, high-performance memories with low power for Arm devices
Key requirements- 2-5 years of circuit design experience with SRAM preferred
- Master's in Electrical Engineering, Computer Engineering, or related field with VLSI emphasis, or Bachelor with relevant experience
- Experience in physical IP design (memories, standard cells, IOs, or PHYs)
- Understanding of memory principles, especially SRAM, and deep sub-micron trade-offs
- Proficiency with Cadence Virtuoso and schematic/layout editing; Spice/FastSpice simulators
- Collaborative, innovation-driven mindset and efficiency-focused approach
- collaborative
- innovative
- efficiency-minded
- SRAM memory design
- memory architectures
- physical IP design
