Overview As Superchip SoC TPM, you orchestrate complex multi-die SoC programs from planning through tapeout. You align die TPMs, functional teams, and engineering leadership to ensure on-time, on-budget delivery with high quality. You navigate cross-die dependencies, governance reviews, and risk mitigation, providing executive-facing visibility and decisions. This role combines deep technical understanding with program leadership to deliver industry-leading SoCs. You drive alignment across organizations and shape execution health and readiness.
Responsibilities- Lead the overall SoC execution plan and master schedule
- Coordinate Die TPMs to maintain cross-die consistency
- Drive cross-die integration, dependencies, and engineering readiness
- Partner with Functional TPMs to supervise execution health and metrics
- Collaborate with Chip Leads, Domain Leads, IP Technical Leads, and Engineering Managers for alignment
- Own program risk management, mitigation, and executive issues
- Lead major SoC governance events (architecture, tapeout readiness, executive reviews)
- Coordinate with IP Management TPM for third-party IP planning and reviews
- Coordinate with Post-Silicon TPM for pre-silicon validation planning and lab readiness
- Collaborate with Solution TPM to align on board readiness and software enablement
- Consolidate program metrics and provide actionable insights for executives
- Supervise resources and engineering costs to align with business objectives
Key requirements- Bachelor's or Master's degree or equivalent in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 20+ years of semiconductor experience
- Minimum 5 years of Technical Program Management leading large-scale SoC programs
- Proven experience delivering sophisticated datacenter-class SoCs
- Strong understanding of the SoC development lifecycle from architecture to tapeout
- Ability to lead large cross-functional teams without direct authority
- Technical expertise in one or more silicon build functional areas
- Strong executive communication
- Collaborative leadership and influence without authority
- Cross-functional collaboration
- Experience with multi-die or chiplet architectures
- Experience leading multiple Die TPMs and Functional TPMs
- Experience with hyperscalers or AI/datacenter silicon
