Overview In this role you will drive verification of complex silicon blocks using SystemVerilog HVL and UVM within a cross-functional team. You will define test plans, build and integrate BFM/Driver/Monitor/Scoreboard, and lead stress and coverage closure to ensure robust design validation. You will work closely with customers, report progress, and contribute to verification closure and debugging efforts. This on-site role offers exposure to high-impact projects within Arrow's semiconductor design services ecosystem.
Compensation / Benefits- Medical, Dental, Vision Insurance
- 401k with Matching Contributions
- Short-Term/Long-Term Disability Insurance
- HSA/HRA Options
- Paid Time Off
- Tuition Reimbursement
Responsibilities- Develop test plans and verification components (BFM/Driver/Monitor/Scoreboard) and integrate in test benches
- Perform stress and corner testing, failure debugging, and gate-level simulations
- Create and maintain assertions and coverage data, drive coverage closure
- Utilize SVTB/UVM for verification and debugging tasks
- Coordinate verification closure with team and communicate progress to customers
- Proactively debug and fix issues, ensure timely verification milestones
- Report progress to customers on a daily or weekly basis
Key requirements- 6+ years of experience in SystemVerilog HVL and C/C++
- 6+ years of experience in UVM
- Proficient in SVTB/UVM, C++ testbench
- Strong debugging and assertion coding skills
- Experience with test plan development and verification closure
- Ability to travel on-site as required
- customer communication
- effective progress reporting
- problem-solving orientation
- SystemVerilog HVL
- C/C++
- UVM
