Overview In this role you help architect and implement custom coherent interconnect IP and LLC blocks for high-performance memory subsystems. You will collaborate with system architects, verification, and design teams to drive RTL design, timing, and power optimizations. You'll own RTL development from architectural exploration to detailed specs and support cross-functional teams to meet PPA goals. The position offers mentorship opportunities and a path to impact Samsung's next-gen interconnects.
Compensation / Benefits- medical, dental, vision
- 401(k)
- tuition assistance
- paid time off
- free onsite lunch
- employee purchase program
Responsibilities- Drive development of custom coherent interconnect IP and LLC blocks
- Partner with architects to define next-generation interconnects and LLC
- Perform microarchitecture development from exploration to specification
- Collaborate with verification to ensure correctness
- Work with implementation to meet timing and area goals
- Produce quality RTL on schedule to meet PPA targets
- Engage performance and power teams to optimize outcomes
- Coordinate with physical design and CAD for implementation details
- Mentor junior engineers
Key requirements- 10+ years with Bachelor's in Computer Science/Computer Engineering or related field, or 8+ years with Master's, or 6+ years with PhD
- Strong RTL design ownership across sub-blocks of coherent interconnect or memory controller/LLC
- Proven architectural-to-RTL experience in high-performance digital designs
- Verilog expertise; solid ASIC design flow knowledge (RTL, verification, synthesis, DFT, timing, floorplanning, ECO, lab debug)
- Knowledge of system caches and directory snoop filter protocols
- Familiarity with on-chip topologies: mesh, ring, crossbar
- Experience leading and mentoring a team
- Understanding of AMBA5 CHI, AMBA4 ACE or AXI interconnects and bus protocols
- Knowledge of memory subsystem and coherent cache design
- Strong communication and collaboration across a global, dynamic team
- Strong communication
- Mentoring capability
- Cross-functional collaboration
- Verilog
- Verilog/VHDL (preferred)
- Scripting (Perl or Python)
