Overview As a hands-on developer, you will own the clocking subsystem of the SerDes IO chiplet, delivering low-jitter PLL/CDR functionality from spec to silicon. You'll port clocking blocks to new nodes and work cross-functionally with datapath, DSP, digital, and firmware teams to meet timing and jitter budgets. Your role combines transistor-level design, verification, and silicon bring-up, shaping the next generation of a high-speed link. This is a technically impactful position at the intersection of software, hardware, and AI infrastructure. You will drive architecture choices that influence performance and reliability in a collaborative, inclusive culture.
Compensation / Benefits- Offers Equity
- Offers Bonus
- Medical/Dental/Vision/401k
- inclusive rewards plan
- wellbeing-focused benefits
- hybrid work arrangement
Responsibilities- Design transistor-level low-jitter frequency synthesis (PLL, VCO, loop filter, divider chain)
- Own phase interpolator and rotation scheme, addressing INL/DNL, glitches, and resolution
- Design high-frequency clock distribution with jitter control, duty-cycle correction, and isolation
- Define and verify CDR architecture and loop dynamics; model behavior and correlate with silicon
- Build phase-noise and jitter budgets; identify jitter sources across the link
- Create verification environment (PSS/HB, transient analysis, Monte Carlo, post-layout) and provide Verilog-A models
- Drive layout of clocking blocks in deep sub-micron nodes with attention to inductor/VCO layout, shielding, and isolation
- Lead silicon bring-up and bench characterization; compare measurements to simulations
Key requirements- Hands-on analog/mixed-signal circuit design with 5+ years of experience
- Proven ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes
- Deep knowledge of PLL architectures, loop dynamics, VCO design, and phase noise theory; understanding of CDR architectures
- Experience with jitter budgeting and decomposition in simulation
- Circuit design in advanced FinFET/GAA nodes using Cadence Virtuoso, Spectre, and post-layout methods
- Silicon bring-up and bench debugging with phase noise analyzers, high-speed scopes, and BERTs
- ownership mindset
- collaboration across cross-functional teams
- problem-solving and rigorous attention to detail
- PLL architecture, phase interpolator, CDR loop design
- VCO design, loop dynamics, phase noise theory
- jitter budgeting and decomposition
