Overview In this role you will help shape Google's next-generation TPUs, driving RTL design, verification, and microarchitecture for AI-focused accelerators. You collaborate with Verification and Physical Design to ensure correctness, timing, and manufacturability while delivering high-performance, power-efficient RTL in SystemVerilog. You will work on chip-to-chip interconnect subsystems and contribute to data-center AI/ML hardware accelerators that power Google's products at scale. This role combines design, architecture, and implementation to push the boundaries of AI hardware.
Compensation / Benefits- bonus target 15%
- equity
- benefits
Responsibilities- Collaborate with Verification to develop test plans, debug RTL, and ensure functional correctness
- Partner with Physical Design to meet timing, area, power, and manufacturability targets
- Define and document microarchitecture for complex TPU digital designs
- Write high-quality, performant SystemVerilog RTL code
- Contribute to RTL IP focusing on chip-to-chip high-speed interconnect subsystems
- Participate in architecture, documentation, and implementation of next-generation data center accelerators
- Support integration of TPU architecture within AI/ML-driven systems
Key requirements- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent practical experience
- 4 years of experience in high-performance ASIC design
- Experience architecting or designing RTL solutions for digital systems
- Experience developing networking IP across MAC/L2/PHY layers
- Experience with high-speed interconnects
- Experience with SystemVerilog RTL coding
- Collaborative in cross-functional teams
- Strong problem-solving and technical communication
- Adaptable to dynamic, fast-paced environment
- SystemVerilog RTL coding
- ASIC/SoC design experience
- Networking IP across MAC, L2, PHY layers
