N
Not Specified Permanent

San Jose, California · USA job

Senior Manager, ASIC Chip Engineering

Nvidia

San Jose, California

Job description

Overview

As ASIC Chip Manager, you will drive the end-to-end execution of SOCs from concept to production, guiding multi-functional teams toward successful silicon first releases. You will own risk identification and mitigation, and coordinate design, DFT, physical design, VLSI, emulation, software, and operations workstreams. Your leadership will shape roadmap decisions and ensure robust bring-up, reliability, and qualification. This role sits at the heart of NVIDIA's pursuit of advanced, safety-conscious custom silicon for client, workstation, embedded, and automotive markets.

Compensation / Benefits
  • equity
  • benefits
  • base salary range: 232,000 USD - 368,000 USD
Responsibilities
  • Drive execution of SOCs from concept to production
  • Coordinate IP design, integration, DFT, physical design, VLSI, emulation, software, and operations teams
  • Identify technical risks and develop mitigation strategies
  • Lead cross-functional teams in a matrixed global organization
  • Provide technical leadership and direction to the team
  • Measure progress with KPIs and communicate status across teams
  • Implement data analytics and automation to improve execution efficiency
  • Lead after-action reviews for continuous process improvement
Key requirements
  • 10+ years in chip development
  • 5+ years managing an SoC or major sub-system
  • Experience in graphics processing, memory, and I/O sub-systems in SOCs
  • Knowledge of front-end (micro-architecture, low power, RTL, verification, emulation) and back-end (physical design, clock/reset, DFT) flows
  • Silicon bring-up, reliability, and qualifications
  • Excellent written, verbal, and technical communication skills
  • Ability to multi-task across projects in a matrixed environment
  • Experience with data analytics and automation in engineering workflows
  • strong leadership
  • cross-functional collaboration
  • problem-solving under complexity
  • SoC development lifecycle
  • front-end flows (micro-architecture, RTL, verification)
  • back-end flows (physical design, DFT)

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