Overview In this role you design and validate hardware blocks, using simulation and analysis to meet power and performance specs. You will build and integrate components into subsystems and collaborate with Verification and Silicon Validation teams to ensure correct functionality. You'll contribute to synthesis decisions, timing closure, and Physical Design for digital blocks, while taking a leadership role on technical projects. This position offers the chance to push hardware innovation for Google's direct-to-consumer products and power high-performance computing experiences.
Compensation / Benefits- bonus target (15%)
- equity
- benefits
Responsibilities- Use simulation, emulation, and power analysis to guarantee power and performance meet specs
- Develop, implement, and maintain design blocks and integrate them into subsystems
- Collaborate with Verification and Silicon Validation teams to verify functionality
- Provide input on synthesis, timing closure, and Physical Design of digital blocks
- Take a leadership role on technical project teams and steer technical direction
Key requirements- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience
- 4 years of experience with digital logic design principles, RTL design concepts, and Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance, and power, as well as low-power design techniques
- leadership
- collaboration
- effective communication
- digital logic design
- RTL design (Verilog/SystemVerilog)
- logic synthesis
