N
Not Specified Permanent

San Jose, California · USA job

Senior ASIC Design Engineer - DFT

Nvidia

San Jose, California

Job description

Overview

Join NVIDIA as a Senior ASIC Design Engineer in DFX to shape architecture and implementation of DFT IPs for next gen SoCs. You'll drive cross functional collaboration across design, verification, and backend teams, aligning features with system goals and pre-/post silicon needs. You'll own DFT design and methodology, from fuse controllers to full chip verification, influencing efficiency and reliability at scale. This role offers hands on impact on groundbreaking semiconductor projects and mentorship for junior engineers. You'll work in a fast paced, collaborative environment that values innovation and technical excellence.

Compensation / Benefits
  • competitive compensation
  • comprehensive benefits
  • equity
  • career advancement opportunities
Responsibilities
  • Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs
  • Develop, deploy, and enhance DFT methodologies for scalability and future product needs
  • Define and align feature sets by working closely with architects, platform, and software teams
  • Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration
  • Create and execute test plans to support both functional and DFT full-chip verification
  • Support post-silicon bring-up and validation efforts including debug and issue resolution
  • Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance
Key requirements
  • 8+ years of experience with Bachelor's degree or 6+ years with Master's in Electrical Engineering or related field
  • 5+ years hands-on experience in SoC architecture, RTL design, and verification
  • Strong proficiency in micro-architecture and RTL development using Verilog (UVM experience is a plus)
  • Deep expertise in DFT design, methodology, and implementation
  • Familiarity with clocking, STA, place & route, and power optimization
  • Experience in post-silicon bring-up on ATE, including pattern formats, test program development, and failure analysis
  • Proficiency in scripting languages such as Python, Perl, or Tcl
  • Excellent communication skills and a collaborative mindset
  • excellent communication
  • collaboration
  • curiosity and problem-solving passion
  • Verilog micro-architecture
  • DFT design and methodology
  • UVM (plus)

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