Overview In this role, you will join the Silicon One development organization to shape DFT for next-generation networking silicon. You'll work with front-end RTL and back-end PD teams to infuse testability early in the design cycle and help drive post-silicon validation. Your work will influence full chip design integration and test strategies across implementation and qualification phases. This role offers a chance to impact scalable, testable hardware platforms at Cisco's AI-era data infrastructure scale.
Compensation / Benefits- medical, dental and vision insurance
- 401(k) plan with matching
- paid holidays and floating holiday
- paid vacation and sick time
- parential leave
- RSU grants
Responsibilities- Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, and diagnostics
- Develop innovative DFT IP in collaboration with multi-functional teams and integrate testability in RTL
- Collaborate with design/verification and PD teams to validate test logic across implementation and post-silicon flows
- Contribute to innovative DFT and physical design aspects for new silicon device models, bare/w stacked dice, and reusable test strategies
- Craft solutions and debug with minimal supervision
- Support post-silicon validation and ATE pattern work
- Participate in cross-functional efforts to drive DFT/quality processes through the entire flow
Key requirements- Bachelor or Master in Electrical or Computer Engineering with at least 7 years of experience
- Experience with DFT, test, and silicon engineering
- Experience with JTAG, Scan, and BIST architectures (including memory BIST and boundary scan)
- Experience with ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime)
- Experience with gate-level simulation and debuggers (VCS and other simulators)
- Post-silicon validation and debug experience; ability to work with ATE patterns (P1687)
- Preferred: Verilog DFT logic/IP integration; DFT CAD development; Test Architecture and Infrastructure
- Verification skills (SystemVerilog, logic equivalency checking, test-timing validation)
- Independent problem solving
- Cross-functional collaboration
- ability to learn quickly and mentor less-experienced teammates
- DFT design and integration
- JTAG/Scan/BIST architectures
- ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime)
