Overview As a Senior Digital Design Engineer within the NVLink Fusion design team, you will shape high-performance, area- and power-efficient RTL blocks for AI infrastructure silicon. You collaborate with chip architects and verification teams to deliver verified, synthesis-clean designs and explore IP options for diverse use cases. Your work enables rack-scale AI connectivity through NVLink Fusion and related protocols, contributing to cutting-edge SoC development.
Compensation / Benefits- equity eligibility
- comprehensive benefits package
- competitive base salary
- opportunity for growth
- global team collaboration
Responsibilities- Analyze architectural requirements and perform trade-offs to deliver RTL blocks with high throughput and efficiency
- Draft micro-architecture specifications, implement in RTL, and ensure full verification and timing closure
- Collaborate with chip architects, verification, formal verification, and SoC integration engineers to meet block goals
- Identify potential IP solutions, assist in selecting, customizing, and integrating IP blocks
Key requirements- Bachelors or Masters in Electrical Engineering or Computer Engineering or equivalent experience
- 5+ years of relevant experience
- Experience with high-speed connectivity protocols (NVLink, PCI-Express, Ethernet, UCIE)
- Proven track record delivering high-bandwidth datapath blocks (data movers, protocol adaptors, NoC, arbiters, schedulers)
- Deep understanding of ASIC design flows and methodology
- Strong analytical and interpersonal skills, excellent teammate
- Strong analytical skills
- Excellent teamwork and collaboration
- Interpersonal communication
- NVLink, PCI-Express, Ethernet, UCIE protocols
- High-bandwidth datapath design (data movers, protocol adaptors, NoC, arbiters, schedulers)
- RTL design, synthesis and timing analysis
