Overview In this role you will help scale silicon-based quantum processors, from qubit process conception to tapeout and fab integration. You will collaborate with qubit, control, system, and foundry teams to define processes and design rules for large-scale quantum chips. The position focuses on bridging quantum physics with semiconductor manufacturing to deliver practical, scalable quantum solutions. You'll work on design automation, PDK development, and routing strategies that enable millions of qubits, supporting Intel's quantum computing roadmap.
Compensation / Benefits- Total rewards package
- Stock bonuses
- Health benefits
- Retirement plans
- Paid vacation
- Career growth opportunities
Responsibilities- Establish qubit processes and design rules with lithography, process integration, measurement, and PDK teams
- Architect standard cell design for qubit and readout elements and related automation
- Develop universal qubit process files, models, and extraction capabilities with TCAD/PDK teams and vendors
- Analyze tradeoffs between quantum error correction schemes and qubit topology with software/control teams
- Create front-end design automation and routing flows for large-scale quantum processors
- Develop automated place-and-route flows and AI-based routing optimization for high I/O counts
- Enable customized EDA tool capabilities and PDK collateral for large-scale routing
- Drive signal integrity analysis to design routing strategies and release customized PDKs
- Perform design validations (DRC, LVS, Extraction) before tape-in
- Co-design interposer interfaces with control and system teams for qubit-ASIC integration
- Design electrical test structures to characterize qubit/interconnect performance and yield
- Incorporate thermal analysis into EDA workflows and PDK toolchains
- Implement PDK collateral into customized environments and workflows
- Engage with external customers to tailor Intel quantum PDK solutions
- Ensure external designs tape out successfully within schedule
Key requirements- Bachelor's degree with 4 years of experience, Master's with 3 years, or Ph.D. in Physics, Electrical Engineering, Cryogenic Engineering, Quantum Technologies, or Quantum Engineering or related field
- Experience with EM modeling and simulation tools for high-speed, high-density interconnects or equivalent
- Experience with design automation flows (SKILL, VSR, MSOA or equivalent) and universal process files
- Proficiency in digital design tools and APR-based routing, with scripting in TCL
- Experience taping out designs on mainstream foundry PDKs and performing DRC, LVS, ERC/PEX validations
- Experience implementing PDK collateral and design flows to support design environments
- Excellent communication and presentation skills
- Strong analytical thinking and problem-solving
- Self-driven with hands-on, can-do mentality
- Electromagnetic modeling and signal integrity/crosstalk analysis
- Standard cell design and design automation flows (SKILL, VSR, MSOA)
- Digital design tools and TCL scripting for APR-based routing
