Overview In this role you will contribute to the complete Physical Design flow for high-speed, low-power ASICs within the Digital ASIC Team. You'll work on complex designs such as GPU, camera interfaces, and modem blocks, driving area, speed, and power targets. You'll collaborate with cross-functional teams to implement timing-closed, robust layouts and verify physical and functional constraints. This position offers the chance to shape cutting-edge silicon technologies in a scalable SoC environment.
Compensation / Benefits- competitive pay range
- annual discretionary bonus program
- annual RSU grants
- comprehensive benefits package
- inclusive accommodations for disabilities
- career development opportunities
Responsibilities- Own the Physical Design flow from netlist to final product deliverables
- Perform place & route, floorplanning, power planning, IR drop analysis, and clock tree synthesis (MMMC)
- Conduct timing optimization and closure, RC extraction, signal integrity, and cross-talk analysis
- Debug timing violations, implement timing fixes and functional ECOs, and fix physical violations
- Apply formal verification and multi-mode/multi-corner considerations in design
- Develop and utilize scripting (Python, Perl/TCL) and C to automate PD tasks
- Understand and apply DFT mode constraints for routing and placement
- Support design verification and power domain analysis throughout the flow
Key requirements- 2-10+ years in physical design or related ASIC roles
- Experience with Cadence Innovus and/or Synopsys Fusion Compiler
- Timing closure experience in Synopsys PTSI
- Formal verification experience
- Power domain analysis and physical verification experience
- strong problem-solving and debugging abilities
- effective collaboration with cross-functional teams
- clear communication of technical concepts
- Cadence Innovus
- Synopsys Fusion Compiler
- Synopsys PTSI
