Overview In this role, you will help shape differentiated architectural innovations for Google's TPU roadmap and drive performance, power, and cost tradeoffs. You will collaborate with Hardware Design, Software, Compiler, ML Model, and Research teams to enable hardware/software co-design and advance ML workloads. You will prototype new hardware features and model performance early to guide production-ready TPU architectures. Join a team pushing the boundaries of AI/ML hardware acceleration and contribute to next-generation TPU systems powering Google-scale applications.
Compensation / Benefits- bonus target (15%)
- equity
- benefits
Responsibilities- Identify and evaluate architectural innovations for the TPU roadmap
- Collaborate with Hardware Design, Software, Compiler, ML Model, and Research teams for co-design
- Characterize and benchmark ML workloads; develop performance models
- Design differentiating features for next-generation TPU architectures
- Prototype hardware features (e.g., instruction extensions, memory layouts) using compiler/runtime stacks
- Develop transaction-level models for early performance estimation and workload simulation
- Optimize accelerator design for performance within power and thermal constraints; explore new power technologies
- Streamline host-accelerator interactions and data transfer; ensure integration across training and inference modes
- Work with XLA compiler, Platforms performance, and system design teams to move innovations to production
Key requirements- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent practical experience
- 5 years of experience in computer architecture, chip architecture, IP architecture, co-design, performance analysis, or hardware design
- Experience developing software in C++ or Python
- Cross-functional collaboration
- Strong problem-solving and analytical thinking
- Effective communication of technical concepts
- Computer architecture and chip architecture
- IP architecture and hardware design
- Co-design and performance analysis
