Overview In this role you will influence future IP directions and own integration strategies within AMD's silicon solutions. You'll balance performance, power, and area while guiding schedules and managing risks across CPU/GPU/SoC domains. You work closely with cross-functional experts to align hardware, firmware, and feature enablement for optimized outcomes. This is an opportunity to shape next-gen architectures and drive impactful, high-performance computing solutions.
Responsibilities- Define IP features and capabilities; own architecture and micro-architecture requirements
- Drive technical specifications for IP blocks and provide direction to execution teams
- Align and optimize hardware (silicon), firmware, and feature enablement for performance and power
- Collaborate cross-functionally to identify risks and resolve architecture-level issues
- Own architecture analysis and support feature-change requests from marketing/business teams
- Partner with design teams on area/floorplan refinement, timing targets, verification test plans, and pre-silicon debug/performance sign-off
- Support post-silicon teams for performance tuning, power optimization, and issue debug
Key requirements- Deep expertise in systems and IP architecture with a focus on SerDes, fabrics, memory subsystems, I/O, clocking, or security
- Experience analyzing CPU/GPU/system-level performance bottlenecks and workloads
- Knowledge of power management, low power microarchitecture, and design methodologies
- Strong cross-functional collaboration and communication skills to influence diverse stakeholders
- excellent communicator
- collaborative and adaptable
- problem-solving and mentoring
- SerDes, fabrics, memory subsystems, I/O, clocking, or security
- CPU/GPU/system-level performance analysis
- power management and low power microarchitecture
