Overview In this role you will advance cycle-accurate performance modeling for Arm interconnect IP, collaborating with architects, RTL, and validation teams to push system performance. You'll deliver high-quality models and test suites, and provide insights to partners building top-tier Arm-powered systems. The position combines hands-on modeling with cross-functional collaboration to shape future interconnect capabilities. This is a chance to contribute to industry-defining IP used across infrastructure, automotive, and mobile markets.
Compensation / Benefits- hybrid working model
- opportunity to work on industry-defining IP
- global reach and impact
- competitive total rewards
- supportive onboarding and accommodations
Responsibilities- Develop cycle-accurate timing and performance models for coherent and non-coherent interconnects
- Drive new feature development and evaluate architectural trade-offs impact on system performance
- Build high-quality performance models for internal analysis and customer evaluation
- Collaborate with internal teams and external customers to deliver insights for high-performing systems
- Design performance test suites, identify bottlenecks, and propose data-driven solutions
Key requirements- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
- Proven experience in SoC performance modeling and/or RTL in the semiconductor industry
- Track record of developing cycle-accurate performance models and evaluating microarchitectural features
- Strong C++ skills for large-scale software development
- Experience with SystemC TLM and proficiency in Python scripting
- proactive attitude
- ownership of problems end-to-end
- curiosity and willingness to learn new domains
- SystemC TLM
- Python scripting
- C++
