Overview In this role you define and drive formal verification strategies for complex IP and SoC designs within AMD's NBIO IOHUB team. You'll lead verification planning, methodology development, and infrastructure, collaborating with architects and engineers to deliver high-quality silicon. You'll influence verification practices across multiple projects and mentor the team. This is a hands-on leadership role at a company powering AI, data centers, and next-gen computing.
Responsibilities- Lead and mentor a team of formal verification engineers across multiple IP and SoC projects
- Define and drive formal verification architecture, methodologies, and development plans with IP architects and design teams
- Develop comprehensive formal verification test plans and verification closure strategies
- Architect, develop, and maintain reusable formal verification environments, components, and infrastructure
- Drive adoption of industry-leading formal verification methodologies and best practices
- Perform formal connectivity verification, deadlock/livelock analysis, and protocol verification for I/O and arbitration-intensive designs
- Apply abstraction, decomposition, and assume-guarantee reasoning to tackle large-scale formal problems
- Debug and triage failures from formal verification and root-cause complex design issues
- Collaborate with design, validation, and post-silicon teams to reproduce and resolve functional issues
- Contribute to verification sign-off activities and ensure high-quality silicon delivery
- Foster technical excellence through coaching and knowledge sharing
Key requirements- Strong understanding of digital design and computer architecture
- Experience with Formal verification (Static and Dynamic), Assertion-based verification, FPV and DPV
- Proficiency with JasperGold CDC/RDC and Connectivity apps
- Experience with SEC/LEC
- Ability to apply abstraction, decomposition, and assume-guarantee reasoning at scale
- Strong design debugging and deep bug hunting skills
- Formal test planning; Formal tools - Jasper, VC-formal
- Knowledge of CPU, GPU, Bus/Noc/Interconnect, Memory Controllers, Cache preferred
- Familiarity with UVM-based simulation environments and bridging formal and simulation-based verification
- SystemVerilog, Verilog or VHDL; Scripting skills are a plus
- BS/MS in Engineering or Computer Science
- Excellent communication, collaboration, and interpersonal skills
- Leadership and mentoring abilities
- Self-motivation and ability to drive initiatives to completion
- Formal verification methodologies (Static and Dynamic)
- Assertion-based verification (ABV)
- FPV and DPV
