Principal HBM Design Architect

In this role, you will lead the design of high-speed DRAM interfaces to the base die within an HBM cube, shaping command/control logic and serialization schemes. You will work with a cross-functional team to evaluate timing, area, and power while driving layout and analog/mixed-signal optimization for next-gen HBM products. The position offers exposure to cutting-edge memory tech and opportunities to influence product direction and architecture. You will translate complex concepts into robust design solutions and communicate findings effectively to peers.

• medical, dental, and vision plans
• robust paid time-off program
• paid holidays
• income protection programs
• paid family leave

• Design high-speed DRAM and Base die interface in HBM cube
• Develop DRAM command and control logic and serialization/deserialization schemes
• Perform circuit simulations using FINESIM, HSPICE, and VERILOG
• Collaborate with data path design on floor planning and full chip testbench
• Analyze timing, area, and power for high-speed DRAM or mixed-signal designs
• Contribute to new HBM product opportunities by assisting with overall design, layout, and optimization of memory, logic, and analog circuits

• Extensive experience with DRAM operation and JEDEC specifications (DDR/LPDDR/GDDR/HBM family)
• Deep expertise in analog and mixed-signal design
• Hands-on experience in DRAM command decoding, bank logic, and RAS/CAS chain design
• Proven track record of innovation and problem-solving in high-performance memory development
• Excellent problem-solving and analytical skills
• Strong collaboration and communication skills with ability to convey technical concepts
• Minimum 10+ years in Memory industry with MS degree or 15+ years with BS
• Job title/level scalable with experience and qualifications

• initiative-taking
• collaboration
• excellent communication
• DRAM operation and JEDEC specifications
• analog and mixed-signal design
• DRAM command decoding, bank logic, RAS/CAS design