Overview In this role you will develop performance models for a high bandwidth AI memory expansion device, collaborating with silicon architects and workload teams. You will explore design tradeoffs, validate performance assumptions, and identify bottlenecks early in development. The work combines hardware and software perspectives to optimize data movement and memory systems at scale. This is an opportunity to shape next gen AI memory architectures and influence cross functional design decisions.
Compensation / Benefits- base salary plus performance bonus and early stage equity
- health, dental, vision, and life insurance
- relocation assistance and visa sponsorship
- daily lunch stipend
- 401k match
- collaborative work environment
Responsibilities- Build and maintain system level performance models for a high bandwidth data movement device in a scale up context
- Model software memory access patterns, data distribution in the network, and on device memory channels
- Collaborate with silicon architects, system designers, and workload owners to align performance expectations
- Identify bottlenecks, scaling limits, and sensitivity points across compute, memory, and interconnects in end to end workloads
- Communicate modeling assumptions, limitations, and conclusions to technical and non technical stakeholders
Key requirements- Bachelor or Master degree in Electrical Engineering, Computer Engineering, or a closely related field
- Ability to quickly learn new ML architectures and build performance models for them
- 5-10+ years of experience in performance modeling for data movement devices (NICs, memory expansion cards like CXL, IPU/DPU, NoC)
- Ability to reason across abstraction layers from architecture to system level performance
- strong communication skills
- collaborative team player
- problem solving with incomplete information
- AI memory systems
- Performance modeling
- Memory expansion devices (NICs, CXL)
