Overview In this role, you will help shape next-generation 3D-stacked high-bandwidth memory architectures for AI workloads. You'll work closely with cross-functional teams to design, simulate, and optimize mixed-signal circuits and power delivery for stacked memories, addressing thermal and interface challenges. Your work will influence future memory products and efficiency at scale. This is a technically rigorous, impact-driven opportunity at a leader in memory technology.
Compensation / Benefits- medical, dental, and vision plans
- paid time-off
- paid holidays
- paid family leave
- bonus and equity as part of compensation
Responsibilities- Design, optimize, and simulate analog and/or mixed-signal circuits
- Architect and design power delivery for high-performance, stacked memories
- Analyze, specify, and prototype on-/off-chip interfaces
- Perform timing, area, power, and complexity analysis for high-performance, low-power circuits
- Define architectures for improved thermal management
- Conduct pathfinding activities for future-generation stacked-memory products
- Compose and maintain architecture documentation
Key requirements- Experience with analog and/or mixed-signal design, including simulation and floorplanning
- Experience with transistor-level simulation (e.g., FineSim, HSPICE) including corner analysis
- Ability to analyze architecture tradeoffs and translate findings into specifications
- Experience with power delivery analysis, tradeoffs, constraints, and challenges
- collaboration
- analytical thinking
- strong communication
- Analog and/or mixed-signal circuit design
- Transistor-level simulation (FineSim, HSPICE)
- Corner analysis
