Overview In this role you will lead end-to-end memory and interconnect architecture for AI accelerators and SoCs. You will define high-bandwidth, low-latency fabrics and memory hierarchies, collaborating with cross-functional teams to translate architecture into hardware. You will model performance and drive design decisions to scale AI workloads across accelerator, host, and memory fabrics. This is a mission-driven opportunity to shape memory subsystem and interconnect strategies for next-generation AI hardware. You will be at the forefront of standards and partner engagements, contributing to robust, high-performance ML platforms.
Compensation / Benefits- base salary plus performance-based bonus
- early-stage equity grant
- health, dental, vision, and life insurance
- relocation assistance and visa sponsorship
- lunch stipend
- 401k match
Responsibilities- Define end-to-end memory and interconnect architectures for AI accelerators, including coherent and non-coherent fabrics and tiered memory hierarchies
- Lead specification and micro-architecture of interfaces and protocols (CXL, NVLink, UALink, RDMA, UCIe, PCIe, ARM CHI) for SoC designs
- Develop performance models and run system-level simulations to evaluate architectural trade-offs
- Collaborate with RTL, verification, firmware, and physical design to implement architecture into hardware blocks
- Drive cross-functional reviews to align interfaces, compliance, and interoperability
- Architect memory subsystems (HBM, DDR, persistent memory) and CXL-attached devices optimized for AI/ML workloads
- Define verification strategies and test plans for coherence, error handling, and performance stress tests
- Mentor engineers and set best practices for memory and interconnect subsystems
- Stay abreast of industry trends and represent the company in standards and partner engagements
Key requirements- 10+ years in ASIC/SoC architecture with focus on memory systems and interconnects for HPC or AI
- Deep knowledge of CXL, NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe protocols
- Experience with memory subsystems (HBM, DDR, persistent memory) and memory controller architecture
- Hands-on experience with AI accelerators and ML hardware architectures
- Strong performance modeling, system-level simulation, latency and bandwidth analysis
- Familiarity with RTL, verification methodologies, and silicon bring-up
- Excellent written and verbal communication; ability to influence across teams
- Proven technical leadership and mentoring track record
- Experience with scripting and modelling tools (Python, C/C++, SystemC) is a plus
- cross-functional collaboration
- clear communication
- mentorship
- CXL
- NVLink
- UALink
