Overview In this role, you will define the compute architecture for MatX's AI accelerators, aligning ISA, memory hierarchy, and interconnect to AI workloads. You'll translate use cases into architectural requirements and perform performance analyses to meet power and area targets. Collaboration with Research, Software, and Hardware teams ensures silicon meets workload needs and scalability. You'll influence test plans, bring-up, and post-silicon debugging, contributing to MatX's mission of rapid, sustainable GenAI at scale.
Compensation / Benefits- 4 weeks PTO (accrued)
- 12 company holidays
- remote work up to 3 weeks
- health: medical, dental, vision
- retirement options with employer contribution
- professional development budget
Responsibilities- Define architecture for AI compute subsystem (ISA, connectivity, memories, control)
- Derive architectural requirements from AI use cases
- Perform analytical and empirical performance analyses
- Collaborate with Research, SW, HW to tailor silicon for workloads and programmability
- Evaluate power, area, and performance tradeoffs with stakeholders
- Support test plan reviews, first-silicon bring-up, and post-silicon debugging
Key requirements- Strong background in computer architecture for AI accelerators, GPUs, TPUs, vector processors, SIMD, or parallel architectures
- Experience translating workloads into hardware architecture
- Solid microarchitecture fundamentals
- First-principles understanding of latency, throughput, utilization, and scalability
- Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs
- Programming, code optimization, or kernel-level performance analysis experience
- Excellent written and verbal communication skills
- Familiarity with performance-optimization techniques in large-scale transformer models is a plus
- Excellent written and verbal communication skills
- Collaborative mindset with cross-functional teams
- Strong problem-solving and analytical thinking
- AI accelerator architectures (ISA, interconnect, memory hierarchies)
- Workload-to-hardware translation
- Microarchitecture fundamentals
