Overview As a Test Architect, you lead test engineering for strategic semiconductor customers, translating device requirements into robust, production-ready test solutions. You collaborate across customers, product, hardware, software, and manufacturing teams to shape test strategies and validation plans. You'll drive reusable approaches that improve quality, test time, and efficiency across programs. This role blends hands-on engineering with customer engagement and technical leadership, shaping Teradyne's test solutions for high-volume manufacturing. Join us to influence critical test architectures and deliver impactful results at scale.
Compensation / Benefits- medical, dental, vision
- Flexible Spending Accounts
- retirement savings plans
- life and disability insurance
- paid vacation & holidays
- tuition assistance
Responsibilities- Serve as the test architecture lead for strategic customers and translate requirements into executable plans
- Define end-to-end test strategies including content, coverage, instrumentation, multisite execution, data logging, correlation, and production release
- Guide implementation through feasibility studies, test plans, silicon debug, characterization, and issue resolution
- Design for measurement accuracy and establish calibration, uncertainty, guard bands, repeatability, and correlation
- Optimize test solutions for coverage, quality, time, throughput, and cost while meeting product requirements
- Develop reusable test methods, patterns, and validation assets; convert recurring needs into scalable capabilities
- Coach and mentor test and software engineers in architecture and disciplined test development
- Represent Teradyne in customer workshops and architecture reviews, communicating risks and tradeoffs clearly
Key requirements- Bachelor in Electrical Engineering
- At least 7 years of semiconductor test engineering experience with strategy definition or technical leadership
- Strong knowledge of automated test equipment, semiconductor devices, test methods, and production constraints
- Experience with test development, silicon bring-up, characterization, correlation, multisite validation, and test time optimization
- Ability to translate requirements and risks into test coverage and explain tradeoffs to diverse audiences
- Experience leading through influence and mentoring across cross-functional teams
- Comfort working with customers during architecture discussions and escalations
- Strong analytical, written, presentation, and facilitation skills
- Located in or willing to relocate to San Jose, CA, with up to 25% travel
- analytical thinking
- clear communication
- collaboration
- semiconductor test
- DFT, BIST, pattern generation
- digital, power, memory, RF, or mixed-signal test
