M
Not Specified Permanent

San Jose, California · USA job

Datacenter Compute SoC Architect

MediaTek

San Jose, California

Job description

Overview

As Datacenter Compute SoC Architect you define and optimize next-generation datacenter SoCs to meet power, performance, and area targets. You will work with cross-functional teams of CPU architects, IP designers, and software engineers to deliver scalable, efficient silicon for cloud and AI workloads. The role combines architecture definition, IP selection, PPA trade-offs, and advanced packaging to enable high-performance data center hardware. This is a leadership-focused position with hands-on RTL and silicon bring-up influence.

Compensation / Benefits
  • performance bonus
  • short and long-term incentive programs
  • comprehensive health insurance
  • life and disability insurance
  • 401K
  • paid holidays
Responsibilities
  • SoC Architecture Definition for next-gen datacenter Compute SoCs, including cores, caches, interconnects, and memory subsystems
  • IP Selection & Integration for PCIe Gen5/6, CXL, DDR5/HBM, NoC, and security enclaves
  • PPA Optimization through design trade-off analyses to meet efficiency targets
  • Advanced Packaging Strategy with packaging teams on multi-die/chiplet architectures and D2D interconnects (UCIe)
  • HW/SW Co-Design with firmware, OS, and cloud software teams to support virtualization and cloud-native workloads
  • Performance Modeling with C++/SystemC models and bottleneck analysis
  • Technical Leadership in architecture specifications, RTL implementation, verification, and silicon bring-up
Key requirements
  • Education: Bachelor's or Master's in Electrical Engineering, Computer Engineering, or Computer Science
  • Experience: 10+ years in SoC/Compute/CPU or system architecture; at least 3 years in high-performance server/datacenter or network processor SoCs
  • Technical Expertise: deep understanding of high-performance CPU architectures (ARM, x86, or RISC-V) and Compute architectures; knowledge of coherent fabrics and interconnects (ARM AMBA CHI, AXI, NoCs); memory hierarchy and main memory technologies (DDR4/5, LPDDR, HBM); high-speed I/O interfaces (PCIe, CXL, Ethernet); strong communication skills
  • Exceptional written and verbal communication
  • Ability to distill complex concepts into clear specifications
  • Cross-functional collaboration
  • CPU architectures (ARM, x86, or RISC-V)
  • Coherent interconnects and NoCs
  • Memory systems (DDR4/5, LPDDR, HBM)

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