A
Not Specified Permanent

Cambridge, Massachusetts · USA job

Principal AI Accelerator Architect Lead

Analog Devices

Cambridge, Massachusetts

Job description

Overview

In this role you drive fundamentally innovative AI compute embedded in silicon, focusing on ultra-low power and deep integration. You will architect system-level designs from concept to detailed specifications and compare computing modalities to advance practical, addressable AI solutions. You'll bridge academia and real-world deployment, navigating physical constraints to ensure robust, scalable implementations. You join a cross-disciplinary team to shape next gen AI accelerators and influence multiple SoC generations with hands-on leadership.

Compensation / Benefits
  • medical, vision and dental coverage
  • 401k
  • paid vacation
  • holidays
  • sick time
  • other benefits
Responsibilities
  • Translate product requirements into end-to-end system architectures for IP blocks, processors, firmware, memory subsystems, and AI compute engines.
  • Explore representations of intelligence beyond traditional digital AI models and architectures.
  • Bridge academic research with real-world deployment under physical constraints such as noise, power, variability, and manufacturability.
  • Lead architecture exploration and collaborate with the modeling team to drive insights and breakthroughs.
  • Define hardware block specifications and interfaces, contributing to modeling and RTL development where appropriate.
  • Collaborate with architecture, design, verification, firmware, and physical design teams to realize architectural intent.
  • Provide technical leadership and mentorship across projects and SoC generations.
Key requirements
  • PhD or Master's degree in Computer Engineering, Electrical Engineering, or related field
  • 10+ years in digital and analog AI accelerator systems architecture for Physical AI or embedded intelligent platforms (robotics/drones/AV)
  • Hands-on experience with digital signal processing and analog/digital neural-network compute architectures
  • Experience mapping AI workloads to compute requirements
  • Proven ASIC design expertise including high-speed and low-power RTL, SystemVerilog for analog compute representation, and familiarity with physical design flows
  • Strong SystemC modeling and virtual prototyping skills for complex system-level models
  • Deep understanding of processor architecture, datapaths, memory hierarchies, interconnects, and chip interfaces
  • Proficiency in C and modeling/simulation languages
  • Excellent written and verbal communication; strong technical leadership and curiosity
  • leadership
  • mentorship
  • strong communication
  • SystemVerilog
  • SystemC
  • RTL development

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