Overview As Principal System Power Management and Performance Architect, you define multi-generation system-level power and performance roadmaps and own the integration strategy for HSIO power management, DVFS, P-states, and low-power features. You will solve ambiguous, cross-domain problems spanning workload behavior, silicon capabilities, firmware policies, and platform constraints, turning them into durable architectures. You collaborate across architecture, ASIC, board/platform, and firmware teams to improve power, performance, and reliability at scale. This role offers a chance to shape datacenter features and drive co-design across NVIDIA's roadmap in a high-impact environment.
Compensation / Benefits- equity
- comprehensive benefits package
- hybrid work (LI-Hybrid)
- competitive salary
- career growth opportunities
- global impact projects
Responsibilities- Define multi-generation roadmaps for system-level power and performance features based on prototyping and cost/benefit analysis
- Own architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features
- Lead system-level boot and IST architecture across complex multi-IP systems
- Drive datacenter-scale power management strategy, including rack-level telemetry and platform state coordination
- Identify and redesign system-level processes (boot/reset flows, low-power entry/exit, control policies) to meet new product requirements
- Serve as the cross-functional technical authority across architecture, ASIC, board/platform, and firmware teams
- Influence decisions beyond own group to optimize power-performance trade-offs
Key requirements- 15+ years of system architecture, development, and validation focused on power and performance-per-watt in datacenter or HPC platforms
- Verifiable history of guiding architecture decisions shipped across multiple silicon programs
- Extensive knowledge of HSIO power management, DVFS, P-states, system boot flows, and low-power architectures
- Strong fundamentals in low-power design and rack-level performance architecture
- Hands-on depth in at least two of: system power management, robust boot flow optimizations, HSIO, memory power management
- Proven ability to introduce a power management architecture/methodology adopted across silicon generations
- Demonstrated AI/agentic workflow practice with disciplined velocity and risk awareness
- Visible technical leadership through patents, publications, or industry recognition
- technical leadership
- cross-functional collaboration
- problem solving under ambiguity
- HSIO power management
- DVFS
- P-states
